Sundance SMT387 User Manual

SMT387 User Manual User Manual; Version 1.0.2, 4/8/04; © Sundance Digital Signal Processing, Inc. 2004

Version 1.0.3 Page 10 of 42 SMT387 User Manual 5. Replace the carrier board in the host system or power on for a stand-alone carrier. SMT387 + DSP

Version 1.0.3 Page 11 of 42 SMT387 User Manual TMS320C6415{xe "TMS320C6201"} The processor will run with zero wait states from internal S

Version 1.0.3 Page 12 of 42 SMT387 User Manual The C60 contains several registers that control the external memory interfaces (EMIFs). {xe "me

Version 1.0.3 Page 13 of 42 SMT387 User Manual The EMIFB CE1 and CE2 space control registers should be programmed with the value 0xFFFFFF03. As the

Version 1.0.3 Page 14 of 42 SMT387 User Manual One limitation of the DSP PCI interface is that it is incapable of byte-oriented reads or writes. Th

Version 1.0.3 Page 15 of 42 SMT387 User Manual FPGA The module can be fitted with a XC2VP7, XC2VP20, or XC2VP30. Only flip-chip FF896 package wil

Version 1.0.3 Page 16 of 42 SMT387 User Manual Figure 3: JTAG Chain on the SMT387 When accessing the board using JTAG, the CPLD can be bypassed a

Version 1.0.3 Page 17 of 42 SMT387 User Manual communication from the PC. The Parallel Cable III supports only parallel port communication from the

Version 1.0.3 Page 18 of 42 SMT387 User Manual SHB SHB Connector The SMT387 includes a single 60-pin connector to provide SHB communication to the

Version 1.0.3 Page 19 of 42 SMT387 User Manual SHB Cable Assembly The cable is custom made by Precision Interconnect and a cable assembly solution

Version 1.0.3 Page 2 of 42 SMT387 User Manual Revision History Date Comments Engineer Version 3/26/04 First released version PTM 1.0.0 3/29/04

Version 1.0.3 Page 20 of 42 SMT387 User Manual Constraint File Signal Names According to the SUNDANCE SHB specification, 5 Byte-interfaces (from 0

Version 1.0.3 Page 21 of 42 SMT387 User Manual RSL RSL Connector The SMT387 includes a single 28-pin (14-pair) RSL connector. The connector is r

Version 1.0.3 Page 22 of 42 SMT387 User Manual Speed grade -7 -6 -5 RSL speed (Gbps) 3.125 3.125 2.0 Table 3: RSL Speed vs. FPGA Speed Grade

Version 1.0.3 Page 23 of 42 SMT387 User Manual Clocks The FPGA clock is provided by the EMIFA of the DSP. This can be configured as ¼ or 1/6 of the

Version 1.0.3 Page 24 of 42 SMT387 User Manual Note: An example of these procedures is available in software package SMT6087. FPGA_PCI_CMD  FPGA_

Version 1.0.3 Page 25 of 42 SMT387 User Manual D4 Red DSP GP0 D5 Red DSP GP1 D6 Red FPGA LED0 D7 Red FPGA LED1 / PCI SATA IDSEL* *FPGA LED1 is us

Version 1.0.3 Page 26 of 42 SMT387 User Manual This module must have 5V supplied through the TIM connectors. In addition, a 3.3V supply is required

Version 1.0.3 Page 27 of 42 SMT387 User Manual Power Consumption Measurements were made on an SMT387 at idle with the standard FPGA configuration l

Version 1.0.3 Page 28 of 42 SMT387 User Manual Serial ATA The Silicon Image 3512 host controller allows for 2x Serial ATA 1.0 compliant interfaces.

Version 1.0.3 Page 29 of 42 SMT387 User Manual Software The software developed to support the SMT387 Data Logger will transfer data between one or

Version 1.0.3 Page 3 of 42 SMT387 User Manual Table of Contents Revision History ...

Version 1.0.3 Page 30 of 42 SMT387 User Manual Prerequisites 1. To run the example you will need: • The Sundance board support package (SMT6025)

Version 1.0.3 Page 31 of 42 SMT387 User Manual Running the Example The example is executed by running Logger.exe. This resets the DSPs, loads the

Version 1.0.3 Page 32 of 42 SMT387 User Manual used. The first few blocks of data read from the SDBs will be discarded to ensure a continuous data

Version 1.0.3 Page 33 of 42 SMT387 User Manual Discs You can select the discs to use by clicking IDE 0 and IDE 1. The discs will be used as follow

Version 1.0.3 Page 34 of 42 SMT387 User Manual Verification Procedures The specification (design requirements) will be tested using the following:

Version 1.0.3 Page 35 of 42 SMT387 User Manual Custom The ordering code for custom configuration is as follows: SMT387–VP20-5-x-Zy Board Type Virt

Version 1.0.3 Page 36 of 42 SMT387 User Manual PCB Layout Details Components placement Figure 10: SMT387 Components placement-Top view

Version 1.0.3 Page 37 of 42 SMT387 User Manual Figure 11: SMT387 Components placement-Bottom view U1: Xilinx FPGA Power Supply U2:

Version 1.0.3 Page 38 of 42 SMT387 User Manual Headers Pinout SHB Header Pin2Integral Ground planePin 1Alignment PinBlade and Beam Design0.5mm

Version 1.0.3 Page 39 of 42 SMT387 User Manual SHB Pinout (LVTTL only).(J2) In the constraints file provided for the SMT387 FPGA, the SHB signals

Version 1.0.3 Page 4 of 42 SMT387 User Manual Half Word Interface (16-bit SHB Interface)... 19

Version 1.0.3 Page 40 of 42 SMT387 User Manual JTAG/Multilinx headers The JTAG/Multilinx headers have the following pinout: TIM ConnectorTIM Conne

Version 1.0.3 Page 41 of 42 SMT387 User Manual Supplies VCC (3.3V, 10 mA, typically) to the cable. system VCC TCK 6 Test Clock. This clock drives t

Version 1.0.3 Page 42 of 42 SMT387 User Manual Safety This module presents no hazard to the user. EMC This module is designed to operate from with

Version 1.0.3 Page 5 of 42 SMT387 User Manual Further details ...

Version 1.0.3 Page 6 of 42 SMT387 User Manual Table of Figures Figure 1: SMT387 Block Diagram...

Version 1.0.3 Page 7 of 42 SMT387 User Manual Physical Properties Dimensions See Physical specifications of TI TIM specification & user’s gui

Version 1.0.3 Page 8 of 42 SMT387 User Manual Introduction Related Documents [1] Sundance High-speed Bus (SHB) specifications – Sundance. http://s

Version 1.0.3 Page 9 of 42 SMT387 User Manual Mechanical Interface: TIM Standard This module conforms to the TIM standard (Texas Instrument Modu