Sundance SMT370v2 User Manual

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999SMT370v2/v3 User Manual

Version 2.0 Page 10 of 46 SMT370v2/v3 User Manual Ressource occupied.The default firmware, as it comes with the board, uses FPGA resources, such as R

Version 2.0 Page 11 of 46 SMT370v2/v3 User Manual ADCs and DAC. The SMT370 is populated with two AD6645s (2 channels) and one AD9777 (dual channel).

Version 2.0 Page 12 of 46 SMT370v2/v3 User Manual other and therefore the two 16-bit data streams can be considered as a single 32-bit data stream. I

Version 2.0 Page 13 of 46 SMT370v2/v3 User Manual 1 -> Flashing under the ADC sampling clock (it can be useful to check that the LED is flashing

Version 2.0 Page 14 of 46 SMT370v2/v3 User Manual you must make sure that you only ever connect links initialising as transmitters to links initialis

Version 2.0 Page 15 of 46 SMT370v2/v3 User Manual three control signals: write enable, request and acknowledge. An SHB bus can alsobe divided into tw

Version 2.0 Page 16 of 46 SMT370v2/v3 User Manual ADC Performance. Description SpecificationAnalogue inputs Maximum voltage 1.2 Volts peak-to-peak (A

Version 2.0 Page 17 of 46 SMT370v2/v3 User Manual The schematics below give details on the ADC input coupling. Both options (AC or DC couplings) are

Version 2.0 Page 18 of 46 SMT370v2/v3 User Manual The following graphs gives the average FFT of sixteen 16K-FFTs processed after capturing data from

Version 2.0 Page 19 of 46 SMT370v2/v3 User Manual DAC Performance. Description SpecificationAnalogue outputs Maximum voltage 1 Volt peak-to-peak Imp

Version 2.0 Page 2 of 46 SMT370v2/v3 User Manual Revision History Date Comments Engineer Version14/02/03 First release PSR 1.008/03/03Details added

Version 2.0 Page 20 of 46 SMT370v2/v3 User Manual Figure 10 - DAC output stage. The following capture shows a 5MHz signal generated by the DAC under

Version 2.0 Page 21 of 46 SMT370v2/v3 User Manual SHB pinout. Pin Signal Pin Signal Pin Signal1 CLK0 21 D19 41 D392 D0 22 D20/ WEN1 42 D403 D1 23 D2

Version 2.0 Page 22 of 46 SMT370v2/v3 User Manual The default FPGA firmware implements 2 16-bit interfaces. FPGA Pinout. ############################

Version 2.0 Page 23 of 46 SMT370v2/v3 User Manual NET "ADC_TRIG" LOC = "T21" ; NET "IIOF_0" LOC = "V11" ; N

Version 2.0 Page 24 of 46 SMT370v2/v3 User Manual NET "CONF_INIT" LOC = "AA19" ; NET "CONF_DIN" LOC = "V18"

Version 2.0 Page 25 of 46 SMT370v2/v3 User Manual NET "SHBB<39>" LOC = "M19" ; NET "SHBB<38>" LOC = "

Version 2.0 Page 26 of 46 SMT370v2/v3 User Manual NET "SHBA<11>" LOC = "J1" ; NET "SHBA<10>" LOC = "J

Version 2.0 Page 27 of 46 SMT370v2/v3 User Manual Connector position. Figure 13 - Connector Location.The diagram below gives the position and the mea

Version 2.0 Page 28 of 46 SMT370v2/v3 User Manual Operating conditions. SafetyThe module presents no hazard to the user. EMC The module is designed t

Version 2.0 Page 29 of 46 SMT370v2/v3 User Manual When the board works in a close or warm environment, Sundance recommends having a fan extractor or

Version 2.0 Page 3 of 46 SMT370v2/v3 User Manual Table of Contents Revision History...

Version 2.0 Page 30 of 46 SMT370v2/v3 User Manual Register settings. Register 0x0 – DAC Register (report to AD9777 datasheet for more details). Bit n

Version 2.0 Page 31 of 46 SMT370v2/v3 User Manual Register 0x1 – DAC register (report to AD9777 datasheet for more details). Note the Bit15 should be

Version 2.0 Page 32 of 46 SMT370v2/v3 User Manual Register 0x2 – DAC register (report to AD9777 datasheet for more details). Bit number DescriptionB

Version 2.0 Page 33 of 46 SMT370v2/v3 User Manual Register 0x3 – DAC register (report to AD9777 datasheet for more details). Bit number DescriptionB

Version 2.0 Page 34 of 46 SMT370v2/v3 User Manual Register 0x4 – DAC register (report to AD9777 datasheet for more details). Bit numberDescription Bi

Version 2.0 Page 35 of 46 SMT370v2/v3 User Manual Register 0x5 – Clock management. Bit number DescriptionBit 31 0Bit 30 1Bit 29 0Bit 28 1Bit 27

Version 2.0 Page 36 of 46 SMT370v2/v3 User Manual FSynthesized = (M/N) MHz - With 500 < M < 250 (binary encoding) and N can take one of the fol

Version 2.0 Page 37 of 46 SMT370v2/v3 User Manual Register 0x6 – Channel selection – Triggers – Decimator for ADCs. Bit number DescriptionBit 31 0B

Version 2.0 Page 38 of 46 SMT370v2/v3 User Manual A Decimation Factor of 0 (default value) does not have any effect on the data flow. When it is set

Version 2.0 Page 39 of 46 SMT370v2/v3 User Manual Register 0x7 – DAC control – Pattern generator. Bit number DescriptionBit 31 0Bit 30 1Bit 29 1B

Version 2.0 Page 4 of 46 SMT370v2/v3 User Manual Operating conditions...

Version 2.0 Page 40 of 46 SMT370v2/v3 User Manual The External Trigger signal is routed from connector J16 to the FPGA. Two clamping diodes avoid too

Version 2.0 Page 41 of 46 SMT370v2/v3 User Manual SHBB works either on 16 or 32 bits (see also SDB_technical_specification_v_2_1.pdf):- 16 bits: each

Version 2.0 Page 42 of 46 SMT370v2/v3 User Manual Register 0xD – FPGA Global Reset. By sending this control word, the FPGA gets reset. Every single r

Version 2.0 Page 43 of 46 SMT370v2/v3 User Manual Register 0xE – DAC Register Read back. SMT370v2:By sending this control word, the FPGA reads back t

Version 2.0 Page 44 of 46 SMT370v2/v3 User Manual of a DAC internal register. The 370 starts by sending out register at address 0x0, and carries on u

Version 2.0 Page 45 of 46 SMT370v2/v3 User Manual Register 0xF – Serial Interfaces load. The DAC and the clock synthesizers have all a Serial Port In

Version 2.0 Page 46 of 46 SMT370v2/v3 User Manual SMT370 package.The SMT370 comes with an install package (SMT6600) that contain examples and a C hea

Version 2.0 Page 5 of 46 SMT370v2/v3 User Manual Figure 13 - Connector Location. ...

Version 2.0 Page 6 of 46 SMT370v2/v3 User Manual Outline description. The SMT370 is a dual high-speed ADC/DAC module offering the following features:

Version 2.0 Page 7 of 46 SMT370v2/v3 User Manual Block Diagram - Architecture.The following diagram shows the architecture of the SMT370.Board Reset2

Version 2.0 Page 8 of 46 SMT370v2/v3 User Manual Architecture Description. The module consists of a Xilinx Virtex-II FPGA, two Analog Devices (14-bit

Version 2.0 Page 9 of 46 SMT370v2/v3 User Manual Two Communication links (ComPorts) following the Texas Instrument C4x standardare connected to the F