Sundance SMT362 User Manual

Sundance Multiprocessor Technology Limited User Manual Form : QCF42 Date : 6 July 2006 Unit / Module Description: What is this all about? Unit / Mod

4.2.7 Virtex 4 FX FPGA This device, a Xilinx XC4VFX, is responsible for the provision of the two SHBs, 6 Com-Ports, and the RSLs. On power-up, this d

4.2.7.3 Com-Ports Figure 1: Default firmware ComPort links.. 4.2.7.4 SHB The SMT362 has two SHB connectors, both of which are connected to DSPA to g

4.2.7.5 PXI An external PXI clock and 4 trigger signals are available on the user defined pins of the TIM connectors. These can be used for a variety

4.2.8 GPIO (General Purpose I/O) Two GPIO signals from each DSP are used to illuminate LEDs as shown here; DSPA DSPB GPIO 14 D3 D5 GPIO 15 D2 D

4.2.9 LEDs Eleven LEDs are present on the SMT362. Their function and position are shown here; LED Function D1 FPGA DONE status (illuminates when the

4.2.10 Ethernet A Marvell 88E1116 PHY is connected to a 1.8V I/O bank of the FPGA. Each of the DSP Ethernet PHY interfaces are also connected to the F

SMT362 connected to the SMT562E for Gigabit Ethernet applications. Note the polarity of each end of the cable. Virtex 4FXMAC MAC MAC MACDSPADSPBMAC

4.2.11 RapidIO and RSLs The FPGA provides 16 RocketIO serial interfaces. These are normally run at 2.5Gbps. Each DSP has 4 SRIO interfaces. Again, th

4.2.12 McBSP & Timers Each DSP has two McBSPs (multi-channel buffered serial port), 0 and 1. McBSP1 from DSPA connected to McBSP1 on DSPB. McBSP

5 Footprint 5.1 Top View User Manual SMT362 Last Edited: 29/04/2009 08:56

Revision History Issue Changes Made Date Initials 1.0 First release. 5/2/07 GKP 1.1 Update 20/6/07 GKP 1.1.1 Added CCS basic info. 2/8/07 GK

5.2 Bottom View User Manual SMT362 Page 20 of 30 Last Edited: 29/04/2009 08:56

6 Support Packages 6.1 Code Composer Studio The C6455 is supported under Texas Instrument’s Code Composer Studio (http://focus.ti.com/dsp/docs/dspsu

7 Physical Properties Dimensions 4.2” 2.5” Weight Supply Voltages +5, +3.3V Supply Current +12V 0 +5V +3.3V -5V 0 -12V 0 MTBF User M

8 FPGA Pin-out (ucf) BOARDCLK AG17 DSPB_EMIF_DATA<21> AM8 CP0_DATA<0> W6 DSPB_EMIF_DATA<22> AB12 CP0

CP2_RDY F8 DSPB_EMIF_DATA<54> AL5 CP2_REQ E8 DSPB_EMIF_DATA<55> AM5 CP2_ACK C13 DSPB

CP5_RDY D7 DSPA_RXD<2> N22 CP5_REQ C7 DSPA_RXD<3> P22 CP5_ACK E14 DSPA

DSPA_EMIF_CTRL<3> AE28 RESET AG18 DSPA_EMIF_CTRL<4> AG23 DSPA_EMIF_CTRL<5> AH23 RGMII_COMA

DSPA_EMIF_DATA<31> AK32 SHBA_D0<2> R26 DSPA_EMIF_DATA<32> AJ31 SHBA_D0<3> T26 DSPA_EMIF_DATA<33

DSPA_GPIO_DX1 AA31 SHBB_D0<9> R8 DSPA_GPIO_FSR1 AA24 SHBB_D0<10> T8 DSPA_GPIO_FSX1 Y24 SHBB

DSPB_EMIF_BE<2> AJ15 DSPB_EMIF_BE<3> AH15 DSPB_EMIF_BE<4> AH5 DSPB_EMIF_BE<5> AJ5 DS

Table of Contents 1 Introduction...

9 Safety This module presents no hazard to the user when in normal use. 10 EMC This module is designed to operate from within an enclosed host system

1 Introduction The SMT362 is a dual processor module. Each TMS320C6455 processor runs at up to 1GHz. This provides a module performance of up to 16GI

2 Related Documents TI TMS320C6455 material (http://focus.ti.com/docs/prod/folders/print/tms320c6455.html). Sundance SHB specification. (ftp://ftp2.

4 Functional Description 4.1 Block Diagram 4xLED4x LVTTL I/O PinsJTAG Header2x SHBConnectors3x RSL Connectors12 lanesTop TIM ConnectorComPorts 0 &am

4.2 Module Description 4.2.1 Mechanical Interface This module conforms to the TIM standard for single width modules. It requires an additional 3.3V po

The following table details this; EMIF A Comment EMIF A Comment 0 Latched at reset. Not used on the 362. 10 Pull-up with 1k0. Used to select MAC

4.2.5 DSP Boot When the module is reset, both DSPs come out of their reset state. DSPA will begin execution of code stored in the flash memory. DSPB i