Sundance SMT350 User Manual

SMT350 User Manual

Version 1.9 Page 10 of 45 SMT350 User Manual Functional Description In this part, we will see the general block diagram and some comments on some

Version 1.9 Page 11 of 45 SMT350 User Manual the inter-module connector (SLB – Sundance LVDS Bus, used in this case as ‘single-ended’). DAC: Digi

Version 1.9 Page 12 of 45 SMT350 User Manual ADC Channels. ADC Main Characteristics. The main characteristics of the SMT350 ADCs are gathered into

Version 1.9 Page 13 of 45 SMT350 User Manual Dual-Channel DAC. DAC Main characteristics. The main characteristics of the SMT350 DAC are gathered in

Version 1.9 Page 14 of 45 SMT350 User Manual Figure 5 - DAC Output Stage. Clock Structure There is one integrated clock generator on the module

Version 1.9 Page 15 of 45 SMT350 User Manual ADCs can both receive the same clock or the fraction of the CDCM7005 input clock (/2, /3, /4, /6, /8 o

Version 1.9 Page 16 of 45 SMT350 User Manual Figure 7 - External Clock. The main characteristics of the SMT350 Clocks are gathered into the follo

Version 1.9 Page 17 of 45 SMT350 User Manual on option (3.3 V PECL). Impedance 50-Ohm. Frequency range 62.5 MHz maximum Delay External Ref. Input t

Version 1.9 Page 18 of 45 SMT350 User Manual The figure underneath illustrates this configuration. The bottom view of the daughter card is shown on

Version 1.9 Page 19 of 45 SMT350 User Manual Some JTAG Lines are also mapped onto this connector to be used in case the Daughter module would have

Version 1.9 Page 2 of 45 SMT350 User Manual Revision History Changes Made Issue Initials 11/10/05 Original Document. 1.0 PSR 18/01/06 Updates

Version 1.9 Page 20 of 45 SMT350 User Manual 21 D-12V0 Digital –12.0 Volts – not used on the SMT350 22 DGND Digital Ground 23 D-12V0 Digital –

Version 1.9 Page 21 of 45 SMT350 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 1.9 Page 22 of 45 SMT350 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 1.9 Page 23 of 45 SMT350 User Manual 77 MspTms Reserved 78 MspTdi Reserved. 79 Msptdo Reserved 80 MspnTrst Reserved Figure 12 – Daug

Version 1.9 Page 24 of 45 SMT350 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 1.9 Page 25 of 45 SMT350 User Manual Control Register Settings The Control Registers control the complete functionality of the SMT350. The

Version 1.9 Page 26 of 45 SMT350 User Manual Memory Map The write packets must contain the address where the data must be written to and the read p

Version 1.9 Page 27 of 45 SMT350 User Manual 0x24 DDS Register 4 – Step Phase Increment LSB Read-back (FPGA Register) DDS Register 4. 0x25 DDS Reg

Version 1.9 Page 28 of 45 SMT350 User Manual Test Register – 0x1. Any 8-bit value written in this register can be read-back to check that the Compo

Version 1.9 Page 29 of 45 SMT350 User Manual ADCA Register 2 – 0x4. For more details, refer to ADS5500 datasheet. ADCA Register 2 – 0x4 Byte Bit

Version 1.9 Page 3 of 45 SMT350 User Manual Table of Contents Physical Properties...

Version 1.9 Page 30 of 45 SMT350 User Manual 1 0 1 All outputs are zeroes 2 1 0 All outputs are ones 3 1 1 Continuous stream of ‘10’ ADCB Re

Version 1.9 Page 31 of 45 SMT350 User Manual DAC Register 2 – 0xA. For more details, refer to DAC5686 datasheet. DAC Register 2 – 0xA Byte Bit 7

Version 1.9 Page 32 of 45 SMT350 User Manual DAC Register 6 – 0xE. For more details, refer to DAC5686 datasheet. DAC Register 6 – 0xE Byte Bit 7

Version 1.9 Page 33 of 45 SMT350 User Manual CDCM7005 Register 2 – 0x12. For more details, refer to CDCM7005 datasheet. CDCM7005 Register 2 – 0x1

Version 1.9 Page 34 of 45 SMT350 User Manual CDCM7005 Register 6 – 0x16. For more details, refer to CDCM7005 datasheet. CDCM7005 Register 6 – 0x1

Version 1.9 Page 35 of 45 SMT350 User Manual Mezzanine Module Converters Temperature (not implemented) – 0x1B Mezzanine Module Converters Temper

Version 1.9 Page 36 of 45 SMT350 User Manual Setting Bit 3 Description 0 0 Internal ADC Trigger set to ‘0’. 1 1 Internal ADC Trigger set to ‘1’

Version 1.9 Page 37 of 45 SMT350 User Manual Firmware Version – 0x1D Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Firmware Versi

Version 1.9 Page 38 of 45 SMT350 User Manual DDS Register 2 – Stop Phase Increment LSB - 0x22 DDS Register 2 – 0x22 Byte Bit 7 Bit 6 Bit 5 Bi

Version 1.9 Page 39 of 45 SMT350 User Manual DDS Register 5 – Step Increment MSB - 0x25 DDS Register 5 – 0x25 Byte Bit 7 Bit 6 Bit 5 Bit 4 B

Version 1.9 Page 4 of 45 SMT350 User Manual ADCB Register 0 – 0x5. ...

Version 1.9 Page 40 of 45 SMT350 User Manual FPGA Design The following block diagram shows how the default FPGA design is structured: Figure 17

Version 1.9 Page 41 of 45 SMT350 User Manual Block of registers This implements what has previously been described in this document. Space availa

Version 1.9 Page 42 of 45 SMT350 User Manual PCB Layout The following figures show the top and bottom view of the main module, the top view of th

Version 1.9 Page 43 of 45 SMT350 User Manual Figure 21 - Daughter Module Component Side. Figure 22 - Daughter Module Solder Side.

Version 1.9 Page 44 of 45 SMT350 User Manual Connectors Description The following table gathers all connectors on the board and describes their fu

Version 1.9 Page 45 of 45 SMT350 User Manual Location on the board Figure 23 - Connectors Location.

Version 1.9 Page 5 of 45 SMT350 User Manual Block of registers ...

Version 1.9 Page 6 of 45 SMT350 User Manual Physical Properties Dimensions 63.5mm x 106.7mm x 18mm Weight 35 grams Supply Voltages Supply

Version 1.9 Page 7 of 45 SMT350 User Manual Precautions In order to guarantee that Sundance’s boards function correctly and to protect the module f

Version 1.9 Page 8 of 45 SMT350 User Manual Introduction Overview The SMT350 is a single width expansion TIM that plugs onto the SLB base module SM

Version 1.9 Page 9 of 45 SMT350 User Manual Possible applications The SMT350 can be used for the following application (this non-exhaustive list